Systolic architectures to evaluate polynomials of degree n using the Horner´s rule

This paper presents the design of two systolic architectures to evaluate polynomials of degree n considering the Horner´s rule. The systolic arrays are based on processing elements that process normalized and non-normalized data. The designed architectures are flexible, parameterized and described by using VHDL. This allows achieving a good trade-off between area, performance and flexibility. The synthesis results show that the proposed architectures can be used as coprocessors for high performance reconfigurable computing.