Title :
8912-bit Montgomery multipliers using radix-8 booth encoding and coded-digit
Author :
Renteria-Mejia, C.P. ; Trujillo-Olaya, V. ; Velasco-Medina, J.
Author_Institution :
Bionanoelectronics Res. Group, Univ. del Valle, Cali, Colombia
fDate :
Feb. 27 2013-March 1 2013
Abstract :
This paper presents the design of 8192-bit Montgomery multipliers based on radix-8 Booth encoding and coded-digit. Both multipliers use a systolic architecture and simultaneously carry out two multiplications. The designs are described in generic structural VHDL, synthesized on the EP4SGX230KF40C2 using Quartus II V.12, and verified using SignalTap. The hardware synthesis and performance results show that the designed multipliers present a good area-throughput trade-off and they are suitable for use into a hardware cryptoprocessor.
Keywords :
cryptography; encoding; hardware description languages; systolic arrays; EP4SGX230KF40C2; Montgomery multipliers; Quartus II V.12; SignalTap; generic structural VHDL; hardware cryptoprocessor; hardware synthesis; radix-8 booth encoding; radix-8 coded-digit; systolic architecture; Adders; Algorithm design and analysis; Arrays; Cryptography; Encoding; Hardware; Booth encoding; Montgomery multiplication; RSA cryptosystem; systolic array;
Conference_Titel :
Circuits and Systems (LASCAS), 2013 IEEE Fourth Latin American Symposium on
Conference_Location :
Cusco
Print_ISBN :
978-1-4673-4897-3
DOI :
10.1109/LASCAS.2013.6519072
