• DocumentCode
    601093
  • Title

    Fast floorplanning with placement constraints

  • Author

    Pinge, S. ; Nain, R.K. ; Chrzanowska-Jeske, Malgorzata

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA
  • fYear
    2013
  • fDate
    Feb. 27 2013-March 1 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Today´s deep sub-micron technology and large complex designs have elevated the need for floorplanning to handle placement constraints. We present a unified method to handle alignment and cluster constraints on sequence pair representation. It helps pruning infeasible solutions on sequence pair and significantly reduces the solution space, therefore speeding up the algorithm. We also present an implementation methodology for fast evaluation of these constraints. Experimental results on MCNC and GSRC benchmarks demonstrate that our approach is 4.6X faster on average, scalable with good packing as compared to other published approaches.
  • Keywords
    integrated circuit layout; GSRC benchmark; MCNC benchmark; alignment constraint; cluster constraint; complex designs; deep sub-micron technology; fast floorplanning; placement constraints; sequence pair representation; Benchmark testing; Clustering algorithms; Heuristic algorithms; Maintenance engineering; Routing; Runtime; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (LASCAS), 2013 IEEE Fourth Latin American Symposium on
  • Conference_Location
    Cusco
  • Print_ISBN
    978-1-4673-4897-3
  • Type

    conf

  • DOI
    10.1109/LASCAS.2013.6519081
  • Filename
    6519081