Title :
Efficient parallel scheduler for circuit simulation exploiting binary link formulations
Author :
Paul, Deleglise ; Achar, Ramachandra ; Nakhla, Michel S. ; Nakhla, Natalie M.
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON, Canada
fDate :
Feb. 27 2013-March 1 2013
Abstract :
As circuit sizes increase, a means to improve the performance of simulations is constantly demanded, without sacrificing the accuracy of the results. To achieve this goal, a new parallel scheduler is presented exploiting binary link formulations that allows modern multi-core processors to achieve superior performance. These improvements are obtained without sacrificing accuracy or resorting to iterative techniques.
Keywords :
circuit simulation; multiprocessing systems; processor scheduling; binary link formulations; circuit simulation; circuit sizes; efficient parallel scheduler; iterative techniques; multicore processors; Circuit simulation; Computational modeling; Equations; Integrated circuit modeling; Mathematical model; Scalability; Vectors;
Conference_Titel :
Circuits and Systems (LASCAS), 2013 IEEE Fourth Latin American Symposium on
Conference_Location :
Cusco
Print_ISBN :
978-1-4673-4897-3
DOI :
10.1109/LASCAS.2013.6519091
