Deterministic ATPG for Low Capture Power Testing

The excessive power consumption during testing has been a critical issue for scan-based designs. It gets even worst in the capture mode. This method combines testability-aware test pattern generation with the scan chain disabling technique for low capture power scan testing. The observability cost in the SCOAP algorithm is purposely skewed to guide most fault effects to a limited number of scan cells. Combined with the subsequent scan chain clustering and scan chain disabling techniques, as many non-used scan chains can be disabled during capture cycles. The required hardware overhead for clock gating is limited. Experimental results for the larger ISCAS´89 benchmark circuits have demonstrated that 75.96% of capture power reduction can be achieved.