DocumentCode :
60145
Title :
Revisiting Vulnerability Analysis in Modern Microprocessors
Author :
Maniatakos, Michail ; Michael, Maria ; Tirumurti, Chandra ; Makris, Yiorgos
Author_Institution :
Dept. of Electr. & Comput. Eng., New York Univ. Abu Dhabi, Abu Dhabi, United Arab Emirates
Volume :
64
Issue :
9
fYear :
2015
fDate :
Sept. 1 2015
Firstpage :
2664
Lastpage :
2674
Abstract :
The notion of Architectural Vulnerability Factor (AVF) has been extensively used to evaluate various aspects of design robustness. While AVF has been a very popular way of assessing element resiliency, its calculation requires rigorous and extremely time-consuming experiments. Furthermore, recent radiation studies in 90 nm and 65 nm technology nodes demonstrate that up to 55 percent of Single Event Upsets (SEUs) result in Multiple Bit Upsets (MBUs), and thus the Single Bit Flip (SBF) model employed in computing AVF needs to be reassessed. In this paper, we present a method for calculating the vulnerability of modern microprocessors -using Statistical Fault Injection (SFI)- several orders of magnitude faster than traditional SFI techniques, while also using more realistic fault models which reflect the existence of MBUs. Our method partitions the design into various hierarchical levels and systematically performs incremental fault injections to generate vulnerability estimates. The presented method has been applied on an Intel microprocessor and an Alpha 21264 design, accelerating fault injection by 15×, on average, and reducing computational cost for investigating the effect of MBUs. Extensive experiments, focusing on the effect of MBUs in modern microprocessors, corroborate that the SBF model employed by current vulnerability estimation tools is not sufficient to accurately capture the increasing effect of MBUs in contemporary processes.
Keywords :
fault diagnosis; integrated circuit design; microprocessor chips; statistical analysis; AVF; Alpha 21264 design; Intel microprocessor; MBU; SBF model; SEU; SFI technique; architectural vulnerability factor; computational cost; design robustness; element resiliency assessment; fault model; incremental fault injection; multiple bit upsets; single bit flip model; single event upset; statistical fault injection; vulnerability analysis; vulnerability estimate; Accuracy; Analytical models; Circuit faults; Computational modeling; Estimation; Latches; Microprocessors; AVF; microprocessor vulnerability; multiple bit upset; statistical fault injection;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2014.2375232
Filename :
6967809
Link To Document :
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