Superior Reliability of Junctionless pFinFETs by Reduced Oxide Electric Field

Author

Toledano-Luque, Maria ; Matagne, Philippe ; Sibaja-Hernandez, Arturo ; Chiarella, T. ; Ragnarsson, Lars-Ake ; Soree, Bart ; Cho, Moonju ; Mocuta, Anda ; Thean, A.

Author_Institution

Logic Device Design Group, imec, Leuven, Belgium

Volume

35

Issue

12

fYear

2014

fDate

Dec. 2014

Firstpage

1179

Lastpage

1181

Abstract

Superior reliability of junctionless (JL) compared with inversion-mode field-effect transistors (FETs) is experimentally demonstrated on bulk FinFET wafers. The reduced negative bias temperature instability (NBTI) of JL pFETs outperforms the previously reported best NBTI reliability data obtained with Si channel devices and guarantees 10-year lifetime at typical operating voltages and high temperature. This behavior is understood through the reduced oxide electric field and lessened interaction between charge carriers and oxide traps during device operation. These findings encourage the investigation of JL devices with alternative channels as a promising alternative for 7-nm technology nodes meeting reliability targets.

Keywords

MOSFET; electric fields; negative bias temperature instability; semiconductor device reliability; silicon; JL devices; NBTI reliability; Si; alternative channel device operation; bulk FinFET wafers; charge carriers; inversion-mode field-effect transistors; junctionless pFinFET; negative bias temperature instability reduction; oxide traps; reduced oxide electric field; size 7 nm; superior reliability; typical operating voltages; CMOS technology; Field effect transistors; FinFETs; Integrated circuit reliability; Negative bias temperature instability; Silicon; CMOS; CMOS.; Reliability; junctionless FET; negative bias temperature instability (NBTI); pinch-off FET (POFET);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2014.2361769

Filename

6932422