• DocumentCode
    601588
  • Title

    Novel bonding and joining technology for power electronics - Enabler for improved lifetime, reliability, cost and power density

  • Author

    Haumann, S. ; Becker, Matthias ; Rudzki, J. ; Eisele, Ronald ; Osterwald, Frank

  • Author_Institution
    Danfoss Silicon Power GmbH, Flensburg, Germany
  • fYear
    2013
  • fDate
    17-21 March 2013
  • Firstpage
    622
  • Lastpage
    626
  • Abstract
    An increase in reliability and lifetime for power semiconductors at the same or lower cost and with the potential for higher power density remain high on the wish list for many Power Electronics Engineers. Power semiconductors continuously improve in current density year over year. However, without parallel enhancements in the thermal stack and the associated bonding and joining technology, significant limitations in harvesting these improvements remain. This is especially true when looking at the potential of SiC or GaN semiconductors where higher operating and switching temperatures are limited only by the available packaging technology. This paper presents a solution for a highly reliable power module concept. It is based on interconnect technology with outstanding reliability while maintaining the so desired design flexibility. For the presented solution, die attach is performed by a low pressure sintering process. The top side interconnects are achieved by using three innovative solutions: a sinterable top metallization, a metal buffer plate joined on top of the chip metallization (Danfoss Bond Buffer - DBB) and finally heavy Copper wire bonds.
  • Keywords
    III-V semiconductors; bonding processes; current density; electronics packaging; gallium compounds; joining processes; power semiconductor devices; semiconductor device metallisation; semiconductor device reliability; silicon compounds; sintering; wide band gap semiconductors; GaN; SiC; bonding technology; chip metallization; copper wire bonds; highly reliable power module concept; interconnect technology; joining technology; low pressure sintering process; metal buffer plate; packaging technology; power density; power electronics engineers; power semiconductor lifetime; power semiconductor reliability; sinterable top metallization; switching temperatures; thermal stack;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Applied Power Electronics Conference and Exposition (APEC), 2013 Twenty-Eighth Annual IEEE
  • Conference_Location
    Long Beach, CA
  • ISSN
    1048-2334
  • Print_ISBN
    978-1-4673-4354-1
  • Electronic_ISBN
    1048-2334
  • Type

    conf

  • DOI
    10.1109/APEC.2013.6520275
  • Filename
    6520275