Title :
PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET
Author :
Lahgere, Avinash ; Sahu, Chitrakant ; Singh, Jawar
Author_Institution :
Dept. of Electron. & Commun. Eng., PDPM Indian Inst. of Inf. Technol. Design & Manuf., Jabalpur, India
Abstract :
This paper presents a new design of dopingless dynamically configurable double-gate tunnel FET (TFET) for process-voltage-temperature (PVT)-aware applications. The dopingless FETs have recently been explored and showed very good electrostatic control over the channel with reduced thermal budget and process complexity. The proposed device makes use of the dopingless concept, but instead of charge plasma, electrostatic doping is used for carrier concentration under the source/drain region that allows dynamic configuration. The 2-D device simulation results show that the proposed device has promising switching behavior and offers significant reduction in PVT variations on different performance metrics, such as subthreshold swing and drive current as compared with a conventional TFET.
Keywords :
carrier density; field effect transistors; semiconductor device models; semiconductor doping; tunnel transistors; 2D device simulation; PVT-aware applications; TFET; carrier concentration; dopingless FET; dopingless dynamically configurable double-gate tunnel FET; drive current; dynamic configuration; electrostatic control; electrostatic doping; process complexity; process-voltage-temperature-aware applications; source-drain region; subthreshold swing; thermal budget; Doping; Energy barrier; Logic gates; Sensitivity; Silicon; Temperature sensors; Tunneling; Band-to-band tunneling (BTBT); CMOS; charge plasma; dopingless; process-voltage-temperature (PVT); process???voltage???temperature (PVT); random dopant fluctuation (RDF); tunnel FETs (TFETs); tunnel FETs (TFETs).;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2015.2446615