Techniques for reducing parasitic loss in switched-capacitor based DC-DC converter

In this paper we propose two techniques for reducing top-plate parasitic loss in a switched-capacitor based DC-DC buck converter using on-chip MOS capacitors. In the first technique, soft connection of substrate of a MOS capacitor prevents the top-plate of the parasitic capacitor from charging and discharging and thereby improves power efficiency of the converter. In the second technique which is suitable for processes with low substrate resistivity, soft connection of the n-well (of the MOS capacitor) reduces the effective top-plate parasitic capacitor and thereby decreases the parasitic loss. A buck converter working in Vdd/2 mode has been implemented in 0.24µm CMOS process for demonstration purpose. The first scheme presents an improvement of 6%–21% in the power efficiency. The second scheme provides power efficiency improvement of 2%–5%. Both the techniques provide a consistent improvement of power efficiency compared to the existing implementation of MOS based flying capacitors, for a wide range of load current.