Title :
Numerical & experimental analysis of bond pad stack structure for wire bond interconnection
Author :
Yeo, Alvin ; Che, F.X.
Author_Institution :
Infineon Technol. Asia Pacific Pte Ltd., Singapore, Singapore
Abstract :
This paper presents a Cu wire bond process simulation methodology, to model the mechanical response of the die bond pad stack structure, where different geometries, materials and designs are examined. Both contact and bonding (i.e. ultrasonic) stages are simulated to mimic the actual wire bond interconnection process. Different failure criteria such as maximum shear stress theory, maximum normal stress theory, and maximum distortion energy theory are discussed, and compared with the experimental failure observed. Simulation result reveals that maximum normal stress occurred after the contact force loading, while maximum shear stress occurred after the ultrasonic load with bond force. The high stress region calculated is consistent with the failure location observed in the experimental results, which is at the interface of Mx-1 to low-k dielectric layer. It is also found that top Cu metallization (i.e. Mx) with “array of metal via” design underneath the bond pad is detrimental to the pad structure. Increasing Al bond pad thickness, or/and implementing pad coating layer are an effective approach for increasing the bond pad stack strength, especially with increased Ni coating/plating thickness.
Keywords :
aluminium alloys; copper alloys; failure analysis; integrated circuit metallisation; integrated circuit reliability; lead bonding; low-k dielectric thin films; numerical analysis; Al; Cu; array of metal via design; bond force; bond pad stack strength; bond pad thickness; coating-plating thickness; contact force loading; die bond pad stack structure; experimental failure analysis; failure criteria; high stress region; low-k dielectric layer; maximum distortion energy theory; maximum normal stress theory; maximum shear stress; maximum shear stress theory; mechanical response model; metallization; numerical analysis; ultrasonic load; wire bond interconnection process; wire bond process simulation methodology;
Conference_Titel :
Electronic Manufacturing Technology Symposium (IEMT), 2012 35th IEEE/CPMT International
Conference_Location :
Ipoh
Print_ISBN :
978-1-4673-4384-8
Electronic_ISBN :
1089-8190
DOI :
10.1109/IEMT.2012.6521820