Title :
Real-time time implementation of iterative decoder and DFE using SHARC processor
Author :
Abdelkareem, A.E.
Author_Institution :
Comput. Sci. & Math. Dept., Tikrit Univ., Tikrit, Iraq
Abstract :
A real-time implementation of bit interleaved coded modulation with iterative decoding (BICM-ID) and a decision feedback equalizer (DFE) receiver is proposed. This receiver is based on processing time optimization, cycle stealing, and efficient internal memory allocation. Moreover, a logarithmic version of symbol-by-symbol maximum a posterior (max-Log-MAP) is introduced with new hardware architecture. ADSP-21364 SHARC Digital Signal Processor (DSP) is used to investigate the proposed implementation in the tank. The experimental results show that the proposed system is attained a stable profile with 30 taps equalizer.
Keywords :
decision feedback equalisers; digital signal processing chips; interleaved codes; iterative decoding; maximum likelihood decoding; modulation coding; optimisation; radio receivers; ADSP-21364 SHARC digital signal processor; BICM-ID; DFE receiver; bit interleaved coded modulation; cycle stealing; decision feedback equalizer receiver; hardware architecture; internal memory allocation; iterative decoding; logarithmic version; max-log-MAP; symbol-by-symbol maximum a posterior; time optimization; Decision feedback equalizers; Decoding; Digital signal processing; Iterative decoding; Random access memory; Real-time systems; Receivers; DSP; Real-Time; SHARC;
Conference_Titel :
Computer Applications Technology (ICCAT), 2013 International Conference on
Conference_Location :
Sousse
Print_ISBN :
978-1-4673-5284-0
DOI :
10.1109/ICCAT.2013.6522039
