• DocumentCode
    602616
  • Title

    Worm-Bubble Flow Control

  • Author

    Lizhong Chen ; Pinkston, T.M.

  • fYear
    2013
  • fDate
    23-27 Feb. 2013
  • Firstpage
    366
  • Lastpage
    377
  • Abstract
    Deadlock-free flow control should be designed with minimal cost, particularly for on-chip designs where area and power resources are greatly constrained. While Bubble Flow Control, proposed a decade ago, can avoid deadlock in VCT-switched tori with only one virtual channel (VC), there has been no working solution for wormhole switching that achieves the similar objective. Wormhole switching allows the channel buffer size to be smaller than the packet size, thus is preferred by on-chip networks. However, wormhole packets can span multiple routers, thereby creating additional channel dependences and adding complexities in both deadlock and starvation avoidance. In this paper, we propose Worm-Bubble Flow Control (WBFC), a new flow control scheme that can avoid deadlock in wormhole-switched tori using minimally 1-flit-sized buffers per VC and one VC in total. Moreover, any wormhole-switched topology with embedded rings can use WBFC to avoid deadlock within each ring. Simulation results from synthetic traffic and PARSEC benchmarks show that the proposed approach can achieve significant throughput improvement and also area and energy savings compared to an optimized Dateline routing approach.
  • Keywords
    benchmark testing; buffer circuits; circuit complexity; concurrency control; multiprocessor interconnection networks; network routing; network topology; network-on-chip; 1-flit-sized buffers; PARSEC benchmarks; VCT-switched tori; WBFC; channel buffer size; deadlock-free flow control scheme; energy savings; on-chip designs; on-chip networks; optimized dateline routing approach; packet size; power resources; starvation avoidance; virtual channel; worm-bubble flow control scheme; wormhole packets; wormhole-switched topology; wormhole-switched tori; Electric breakdown; Resource management; Routing; Switches; System recovery; System-on-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on
  • Conference_Location
    Shenzhen
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4673-5585-8
  • Type

    conf

  • DOI
    10.1109/HPCA.2013.6522333
  • Filename
    6522333