Title :
An efficient BCH decoder with 124-bit correctability for multi-channel SSD applications
Author :
Hung-Yuan Tsai ; Chi-Heng Yang ; Hsie-Chia Chang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ. Hsinchu, Hsinchu, Taiwan
Abstract :
This paper presents a low latency and area-efficient architecture for key equation solver (KES) in decoding BCH codes. We modify simplified inversionless Berlekamp-Massey (SiBM) algorithm by rescheduling initial value and removing the idle part during computation. Compared with the original SiBM algorithm, our new architecture implemented in BCH (18244, 16384;124) code can save 42% gate-count within t cycles. Moreover, the proposed KES can simultaneously support 8channel syndrome generators and Chien search logics to achieve 12.6Gb/s throughput under 198MHz operation frequency.
Keywords :
BCH codes; decoding; 8-channel syndrome generators; BCH code decoding; Chien search logics; SiBM algorithm; bit rate 12.6 Gbit/s; efficient BCH decoder; frequency 198 MHz; key equation solver; low-latency area-efficient architecture; multichannel SSD application; simplified inversionless Berlekamp-Massey algorithm;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
DOI :
10.1109/IPEC.2012.6522627
