DocumentCode :
602670
Title :
A 0.1-1.5 GHz 8-bit inverter-based digital-to-phase converter using harmonic rejection
Author :
Ming-Shuan Chen ; Hafez, Amr Amin ; Chih-Kong Ken Yang
Author_Institution :
Univ. of California, Los Angeles, Los Angeles, CA, USA
fYear :
2012
fDate :
12-14 Nov. 2012
Firstpage :
145
Lastpage :
148
Abstract :
In this paper, a 0.1-1.5 GHz 8-bit inverter-based digital-to-phase converter (DPC) is proposed. Conventional inverter-based DPC suffers from poor linearity and limited output frequency range. To mitigate the linearity problem and extend the output frequency range, we propose to use harmonic rejection (HR) filter to cancel out the 3rd- and 5th-order harmonics of the phase interpolated signal. The residual INL and DNL can be further eliminated by nonlinear interpolation technique. Designed and fabricated in 65-nm CMOS technology, the DPC demonstrates a maximum INL and DNL of 2.18 and 0.89 LSB while consumes a power of 4.3 mW and occupies 0.06 mm2 area.
Keywords :
CMOS integrated circuits; digital-analogue conversion; filters; harmonics suppression; interpolation; invertors; CMOS technology; DPC; HR filter; frequency 0.1 GHz to 1.5 GHz; harmonic rejection filter; inverter-based digital-to-phase converter; nonlinear interpolation technique;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
Type :
conf
DOI :
10.1109/IPEC.2012.6522646
Filename :
6522646
Link To Document :
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