A 1-GHz, 17.5-mW, 8-bit subranging ADC using offset-cancelling charge-steering amplifier

A 1-GHz, 17.5-mW, 8-bit subranging ADC was fabricated using 65-nm CMOS technology. We adopt an analog centric approach differing from the digital foreground calibration to reduce power dissipation. An offset cancelling charge-steering amplifier and the capacitive averaging technique effectively reduce the offset, noise, and power dissipation. Moreover, the compensation circuit for the noise current from the comparator can also reduce the power dissipation. The test chip fabricated in 65-nm digital CMOS technology shows a high-sampling rate of 1 GHz and low-power dissipation of 17.5 mW. This chip achieved the FOM of 118 fJ/conv.-step.