Title :
A 9b 1GS/s 27mW two-stage pipeline ADC in 45nm SOI-CMOS
Author :
Pernillo, Jorge ; Flynn, Michael P.
Author_Institution :
Dept. of EECS, Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
A novel, 9b 1GS/s 2-stage pipeline ADC architecture enables high performance with a low-gain op-amp and poor accuracy in the sub-ADC comparators. A reduced MDAC gain of two relaxes the op-amp gain and bandwidth requirements by a factor of 5.7. Deliberate and random comparator mismatch set the trip-points in the 2nd stage flash sub-converter and decouples performance from matching requirements. Digital trimming of a delay chain eliminates mismatch in the sampling paths to provide a simple, low power alternative to a dedicated front-end SAH. The ADC achieves an ENOB of 7.4b at Nyquist, consumes 27mW from a 1.0V supply, yielding an FOM of 160fJ/conversion-step.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; silicon-on-insulator; 2-stage pipeline ADC architecture; SOI-CMOS; Si; delay chain digital trimming; front-end SAH; low-gain op-amp; mismatch elimination; power 27 mW; random comparator mismatch; reduced MDAC gain; second-stage flash sub-converter; size 45 nm; sub-ADC comparators; two-stage pipeline ADC architecture; voltage 1.0 V;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
DOI :
10.1109/IPEC.2012.6522652
