A dynamic resource controller with network-on-chip for a 10.5nJ/pixel object recognition processor

This paper presents a dynamic resource controller (DRC) with network-on-chip (NoC) for an energy-efficient multi-core processor. A total 21 cores in 5 local voltage/frequency islands (VFIs) can be controlled by dynamic resource management (DRM) with the proposed workload-utilization product based prediction model. And a 0.31mm² compact 8×8 NoC switch is designed to reduce unnecessary ~24% power dissipation of each VFI by adopting DVFS and the bandwidth regulation. As a result, thanks to 42% reduction of power-delay product by DRM-based NoC architecture, the 32 mm² multi-core processor, fabricated 0.13μm CMOS process, achieves 10.5nJ/pixel efficiency, 3.54x improvement compared to state-of-the-art object recognition processors.