A 7.5mW 9MHz CT ΔΣ modulator in 65nm CMOS with 69 dB SNDR and reduced sensitivity to loop delay variations

This paper presents a 3^rd-order, 3-bit continuous-time (CT) ΔΣ modulator for an LTE radio receiver. By adopting a return-to-zero (RZ) pulse in the innermost DAC, the modulator shows a reduced sensitivity to loop-delay variations, and the additional loop delay compensation usually needed in CT modulators can be omitted. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 mm × 0.4 mm. It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, while consuming 7.5 mW from a 1.2 V supply.