A 22.4 μW 80dB SNDR ΣΔ modulator with passive analog adder and SAR quantizer for EMG application

Author

Zhijie Chen ; Yang Jiang ; Chenyan Cai ; He-Gong Wei ; Sai-Weng Sin ; Seng-Pan, U. ; Zhihua Wang ; Martins, Rui P.

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2012

fDate

12-14 Nov. 2012

Firstpage

257

Lastpage

260

Abstract

A Feed-Forward (FF) multi-bit ΣΔ modulator with passive analog adder and 4-bit Successive Approximation (SA) quantizer is presented. The modulator covers the 10KHz bandwidth according to electromyography application. The design utilizes the same DAC array of the SAR quantizer to realize analog summation for the FF signal, which significantly reduces the power dissipation and the silicon area. The modulator operates at 1MS/s with IV supply. The prototype chip implemented in 65nm CMOS achieves 80dB SNDR and 81dB DR with 22.4μW power consumption. The Figure of Merit (FoM) is 0.13 pJ/conv.-step.

Keywords

CMOS integrated circuits; adders; biomedical electronics; electromyography; feedforward; medical signal processing; passive networks; power consumption; sigma-delta modulation; CMOS; DAC array; EMG application; FF signal; FoM; SA quantizer; SAR quantizer; SNDR ΣΔ modulator; analog summation; bandwidth 10 kHz; electromyography application; feed-forward multibit ΣΔ modulator; figure of merit; noise figure 80 dB; passive analog adder; power 22.4 muW; power consumption; power dissipation; size 65 nm; successive approximation; word length 4 bit; ΣΔ modulator; SAR quantizer; passive analog adder;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian

Conference_Location

Kobe

Type

conf

DOI

10.1109/IPEC.2012.6522674

Filename

6522674