• DocumentCode
    602777
  • Title

    Low cost TSV integration for advanced packaging technologies

  • Author

    Morikawa, Yasuhiro ; Murayama, Takahide ; Sakuishi, Toshiyuki ; Tanaka, A. ; Nakamuta, Y. ; Suu, Koukou

  • Author_Institution
    Inst. of Semicond. & Electron. Technol, ULVAC, Inc., Shizuoka, Japan
  • fYear
    2012
  • fDate
    10-12 Dec. 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In recent years, “2.5D silicon interposers” and “Full 3D stacked” technology for high-performance LSI has attracted much attention since this technology can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked LSI. 2.5D and 3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. The novel etching technology has provided for TSV fabrication which is the epoch-making and practical new technology without “Bosch” method. This new etch technology is “direct etching” method. So far, anisotropic and high Si etch rate with highly photo-resist selectivity is a tall order, but new direct etching can achieve higher than aspect ratio above 10 at the etching speed that is more than 10um/min in TSV of 10um diameter. Of course the selectivity of photo-resist is realized more than 1:30, and the sidewall is the smooth finish less than 50 nm. The direct etch is environment conscious process. This is because it does not use fluorocarbon gases in direct Si etching, which main gases are SF6 and O2. Therefore, this direct etch process is lower cost than gas switching process. In addition, the smooth sidewall has also brought about low cost of deposition processes for PE-CVD and PVD.
  • Keywords
    SF6 insulation; coating techniques; elemental semiconductors; etching; integrated circuit interconnections; integrated circuit packaging; large scale integration; parallel processing; photoresists; power consumption; silicon; stacking; three-dimensional integrated circuits; 2.5D integration; 2.5D interposers; 2D devices; 3D integration; Bosch method; PE-CVD; PVD; SF6; TSV fabrication; advanced packaging technologies; anisotropic rate; deposition processes; direct etching; direct etching method; environment conscious process; epoch-making; etch rate; etching speed; etching technology; fluorocarbon gases; full 3D stacked technology; high-performance LSI; low cost TSV integration; parallel processing; photoresist selectivity; stacked LSI; through Silicon via;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    CPMT Symposium Japan, 2012 2nd IEEE
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4673-2654-4
  • Type

    conf

  • DOI
    10.1109/ICSJ.2012.6523417
  • Filename
    6523417