• DocumentCode
    602793
  • Title

    Study of the insertion loss of a differential pair of through holes for the 25-Gbps serial interconnect

  • Author

    Shinkai, G. ; Muraoka, S. ; Yagu, M. ; Uematsu, Yutaka ; Osaka, Hideki

  • Author_Institution
    Yokohama Res. Lab., Hitachi Ltd., Yokohama, Japan
  • fYear
    2012
  • fDate
    10-12 Dec. 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    To design future high-speed interconnects that operate above 25 Gbps, accurate scattering parameters (s-parameters) of structures, such as through holes, are necessary. We estimated the s-parameters of a differential pair of through holes by using the de-embedding technique to eliminate undesirable loss and delay in the feed lines connected to the through holes. By comparing this insertion loss and the estimated insertion loss of a corresponding electromagnetic (EM) simulation model, we found that the distance between the center of the drill holes and the center of their clearance could be a reason for the increase in the insertion loss of the through holes in addition to the open stub effect above 20 GHz. We also discuss the reason for the error in the de-embedding from the viewpoint of measurement repeatability. We estimated contact resistance, parasitic capacitance, and parasitic inductance at the air coplanar (ACP) probe tips from the measured s-parameters. The result shows that these parameters varied about 0.1 Ω, 0.1 nH, and 0.05 pF due to reasons such as the contact condition or the flatness of the PCB. To mitigate these parasitic lumped elements, probes with smaller tips are preferable when we measure the s-parameters of structures for de-embedding.
  • Keywords
    S-parameters; electromagnetic wave scattering; integrated circuit interconnections; EM simulation model; PCB; S-parameter; air coplanar; bit rate 25 Gbit/s; contact resistance; deembedding technique; differential pair; drill holes; electromagnetic simulation model; high-speed interconnects; insertion loss; open stub effect; parasitic capacitance; parasitic inductance; parasitic lumped element; scattering parameter; serial interconnect; through holes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    CPMT Symposium Japan, 2012 2nd IEEE
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4673-2654-4
  • Type

    conf

  • DOI
    10.1109/ICSJ.2012.6523463
  • Filename
    6523463