• DocumentCode
    602802
  • Title

    Si based tunnel field effect transistors: Recent achievements

  • Author

    Mantl, Siegfried ; Knoll, Lars ; Schmidt, Martin ; Richter, Simon ; Nichau, A. ; Trellenkamp, Stefan ; Schafer, Andreas ; Wirths, Stephan ; Blaeser, Sebastian ; Buca, Dan ; Qing-Tai Zhao

  • Author_Institution
    Peter Grunberg Inst. 9v, Forschungszentrum Julich, Julich, Germany
  • fYear
    2013
  • fDate
    19-21 March 2013
  • Firstpage
    15
  • Lastpage
    20
  • Abstract
    Recent achievements of silicon based tunnel field effect transistors (TFETs) and remaining major challenges are overviewed. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the heart of the device. Dopant segregation from ion implanted ultrathin silicide contacts proved as viable method to achieve steep tunneling junctions. This avoids defect generation by direct implantation into the junction and thus minimizes the risk of trap assisted tunneling. The method was applied to strained silicon, specifically to nanowire array transistors. This enabled the realization of TFETs with fairly high currents and first complementary TFET inverters with sharp transitions and good static gain, even at very low drain voltages of VDD = 0.2 V. These achievements suggest a considerable potential of TFETs for ultralow power applications. Some novel concepts, e.g. to enlarge the tunneling area by “line tunneling”, are addressed. A benchmarking figure summarizes the present status.
  • Keywords
    elemental semiconductors; field effect transistors; invertors; ion implantation; low-power electronics; nanowires; silicon; tunnel transistors; BTBT junctions; Si; band to band tunneling junctions; complementary TFET inverters; direct implantation; dopant segregation; ion implanted ultrathin silicide contacts; line tunneling; nanowire array transistors; steep tunneling junctions; tunnel field effect transistors; ultralow power applications; voltage 0.2 V; Benchmark testing; CMOS integrated circuits; Electric potential; Logic gates; Silicon; Transistors; Tunneling; Tunnel-FET; inverter; strained Si Nanowire; subthreshold slope; ultralow power electronics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Ultimate Integration on Silicon (ULIS), 2013 14th International Conference on
  • Conference_Location
    Coventry
  • Print_ISBN
    978-1-4673-4800-3
  • Electronic_ISBN
    978-1-4673-4801-0
  • Type

    conf

  • DOI
    10.1109/ULIS.2013.6523480
  • Filename
    6523480