Impact of the statistical variability on 15nm III–V and Ge MOSFET based SRAM design

Author

Si-Yu Liao ; Towie, E.A. ; Balaz, D. ; Riddet, C. ; Cheng, Binjie ; Asenov, Asen

Author_Institution

Device Modelling Group, Univ. of Glasgow, Glasgow, UK

fYear

2013

fDate

19-21 March 2013

Firstpage

133

Lastpage

136

Abstract

The use of III-V and Ge as channel materials is a feasible alternative to Si for the next generation of planar CMOS. We present a set of BSIM4 compact models for III-V and Ge Implant Free Quantum Well (IFQW) transistors which are extracted from well-calibrated TCAD simulations that include the impact of process induced statistical variability. We consider the design of 6T-SRAM using this simulation approach, and investigate the impact of process variability on the memory cell performance. The optimized cell design solutions are presented and discussed.

Keywords

CMOS memory circuits; III-V semiconductors; MOSFET; germanium; semiconductor device models; statistical analysis; 6T-SRAM; BSIM4 compact models; Ge; IFQW transistors; III-V MOSFET; SRAM design; channel materials; implant free quantum well transistors; memory cell; optimized cell design solutions; planar CMOS; statistical variability; well-calibrated TCAD simulations; CMOS integrated circuits; CMOS technology; MOSFET; Robustness; Semiconductor device modeling; III–V; MOSFET; SRAM; compact model; germanium; variability;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (ULIS), 2013 14th International Conference on

Conference_Location

Coventry

Print_ISBN

978-1-4673-4800-3

Electronic_ISBN

978-1-4673-4801-0

Type

conf

DOI

10.1109/ULIS.2013.6523531

Filename

6523531