• DocumentCode
    602898
  • Title

    Min-cut based leakage power aware scheduling in high-level synthesis

  • Author

    Nan Wang ; Song Chen ; Yoshimura, Tetsuzo

  • Author_Institution
    Grad. Sch. of IPS, Waseda Univ., Tokyo, Japan
  • fYear
    2013
  • fDate
    4-6 March 2013
  • Firstpage
    164
  • Lastpage
    169
  • Abstract
    In this paper, we address the problem of scheduling operations into control steps with dual threshold voltage (dual-Vth) technique under timing and resource constraints. We present a min-cut based algorithm for leakage power optimization. The proposed algorithm first initializes all the operations to high-Vth, then iteratively shorten the critical path delay by reassigning the set of operations covering all the critical paths to low-Vth until the timing constraints are met. A modified force-directed scheduling is implemented to schedule operations and to adjust threshold voltage assignments with consideration of resource constraints. During this procedure, mobility overlap graph (MOG) is constructed based on the mobilities of high-Vth operations. To guarantee the resource constraints are satisfied, operations´ threshold voltages are adjusted by computing the min-cut of MOG. Experimental results show that our method performs better both in running time and leakage power reduction compared with MWIS_heuristic [3].
  • Keywords
    graph theory; high level synthesis; optimisation; power aware computing; processor scheduling; MOG; MWIS_heuristic; control steps; critical path delay; dual threshold voltage technique; dual-Vth technique; force-directed scheduling; high-level synthesis; leakage power optimization; leakage power reduction; min-cut based algorithm; min-cut based leakage power aware scheduling; mobility overlap graph; resource constraints; scheduling operations; threshold voltage assignments; timing constraints; Delays; Processor scheduling; Schedules; Scheduling; Sensitivity; Threshold voltage; dual-Vth; force-directed scheduling; leakage power; max-flow min-cut;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ISQED), 2013 14th International Symposium on
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1948-3287
  • Print_ISBN
    978-1-4673-4951-2
  • Type

    conf

  • DOI
    10.1109/ISQED.2013.6523605
  • Filename
    6523605