Title :
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs
Author :
Chenyun Pan ; Ceyhan, Ahmet ; Naeemi, Azad
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.
Keywords :
CMOS integrated circuits; III-V semiconductors; benchmark testing; field effect transistors; indium compounds; microprocessor chips; nanowires; semiconductor device models; tunnel transistors; CMOS devices; InAs; ON/OFF current; TFET; benchmarking; device-level models; input capacitance; multi-core processors; nanowire based gate-all-around tunnel FET; power density; single-core processors; system-level models; system-level optimization; CMOS integrated circuits; Density measurement; Logic gates; Multicore processing; Power system measurements; Throughput; Tunneling; Tunneling FET; energy × execution time; throughput;
Conference_Titel :
Quality Electronic Design (ISQED), 2013 14th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-4951-2
DOI :
10.1109/ISQED.2013.6523610
