Title :
Input-aware statistical timing analysis-based delay test pattern generation
Author :
Bao Liu ; Lu Wang
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Texas at San Antonio, San Antonio, TX, USA
Abstract :
Delay test pattern generation has emerged as an increasingly critical problem in high performance VLSI designs. Existing techniques find timing critical paths by STA or SSTA, apply a traditional ATPG algorithm subsequently and find the test patterns. In this paper, we propose a new delay test pattern generation method, which finds timing critical paths by more accurate input-aware statistical timing analysis, achieves input patterns by back-tracing, and verifies the estimated timing critical paths under the input patterns by logic simulation. Our experimental results based on 9 ISCAS´89 benchmark circuits show that the state-of-the-art SSTA-TQM-BnB technique achieves an average of 57.83%, 54.50%, and 69.91% delay fault coverage, while our SPSTA-DTPG technique achieves an average of 67.83%, 71.39%, and 77.53% delay fault coverage for a test size of 50, 100, and 200, respectively.
Keywords :
VLSI; automatic test pattern generation; delays; integrated circuit design; statistical analysis; ATPG algorithm; ISCAS´89 benchmark circuits; SPSTA-DTPG technique; SSTA-TQM-BnB technique; STA; back-tracing; delay fault; delay test pattern generation method; high performance VLSI designs; input-aware statistical timing analysis; logic simulation; static timing analysis; timing critical paths; Automatic test pattern generation; Circuit faults; Delays; Estimation; Logic gates; Very large scale integration;
Conference_Titel :
Quality Electronic Design (ISQED), 2013 14th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-4951-2
DOI :
10.1109/ISQED.2013.6523651