Title :
Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology
Author :
Beringuier-Boher, Noemie ; Hely, D. ; Beroulle, V. ; Damiens, J. ; Candelier, P.
Author_Institution :
Grenoble-INP LCIS, Valence, France
Abstract :
With the increasing diffusion of multi-purpose systems such as smart phones and set-top boxes, security requirements are becoming as important as power consumption and silicon area constraints in SoCs and ASICs conception. In the same time, the complexity of IPs and the new technology nodes make the security evaluation more difficult. Indeed, predicting how a circuit behaves when pushed beyond its specifications limits is now a harder task. While security concerns in software development and digital hardware design are very well known, analog hardware security issues are not really studied. This paper first introduces the security concerns for analog and mixed circuits and then presents a vulnerability analysis methodology dedicated to them. Using this methodology, the security level of AMS SoC and Analog IP is increased by evaluating objectively its vulnerabilities and selecting appropriated countermeasure in the earliest design steps.
Keywords :
analogue integrated circuits; circuit complexity; cryptography; integrated circuit reliability; microprocessor chips; mixed analogue-digital integrated circuits; system-on-chip; AMS SoC security level; ASIC; IP complexity; analog IP security level; analog hardware security issues; mixed IP; mixed circuits; multipurpose systems; security evaluation; security requirements; vulnerability analysis methodology; Circuit faults; Clocks; IP networks; Power supplies; Security; System-on-chip; Voltage-controlled oscillators; Analog and Mixed IP; Methodology; Security; Vulnerability analysis;
Conference_Titel :
Quality Electronic Design (ISQED), 2013 14th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-4951-2
DOI :
10.1109/ISQED.2013.6523662