Title :
A Successive Approximation A/D Converter Using Generalized Non-Binary Algorithm
Author :
Kurisu, Y. ; Sasaki, T. ; Waho, T.
Author_Institution :
Dept. of Inf. & Commun. Sci., Sophia Univ., Tokyo, Japan
Abstract :
An 8-bit successive approximation analog-to-digital converter (SA ADC) has been designed and fabricated by using a 0.18-μm technology. A generalized non-binary algorithm has been used to enhance operation speed by relaxing the settling constraint of the DAC output. A split-capacitor array with a monotonic switching scheme has also been incorporated to reduce the power consumption. Transistor-level simulation shows an effective number of bits (ENOB) of 7.91 bits under a Nyquist condition with a sampling frequency of 2 MHz. Fabricated chip operates successfully, proving the design principle.
Keywords :
analogue-digital conversion; DAC output settling constraint; Nyquist condition; SA ADC; fabricated chip; frequency 2 MHz; generalized nonbinary algorithm; monotonic switching scheme; operation speed enhancement; power consumption reduction; size 0.18 mum; split-capacitor array; successive approximation A-D Converter; successive approximation analog-to-digital converter; transistor-level simulation; Approximation algorithms; Approximation methods; Arrays; CMOS integrated circuits; Capacitors; Power demand; Switches;
Conference_Titel :
Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on
Conference_Location :
Toyama
Print_ISBN :
978-1-4673-6067-8
Electronic_ISBN :
0195-623X
DOI :
10.1109/ISMVL.2013.9
