Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI

A novel dual-supply-voltage technique is proposed for a low-power multiple-valued VLSI without decreasing speed. A high-supply voltage is required to generate multiple-valued voltage signals in a current-voltage converter, and a low-supply voltage is used to generate binary voltage signals in a comparator whose speed is not decreased by the low-supply voltage. Moreover, level shifters used to prevent direct-path currents in the conventional dual-V_DD CMOS circuits are not necessary to be provided because of constant current flow in the multiple-valued source-coupled logic circuits. As a result, the power consumption of a cell using dual-supply voltages for a multiple-valued reconfigurable VLSI is reduced to 79% in comparison with that of the cell using a single-supply voltage.