FPGA implementation and verification of Reed-Solomon (31, 15, 8) code in SDR system

This study used the LabView FPGA to implement the Reed-Solomon codes (R-S code) on the NI SDR PXIe-5641R FPGA module. Besides providing a detailed discussion on the encoding and decoding mechanism of R-S code, this study completed software simulation and hardware verification of R-S (31, 15, 8) code. When the error probability is 10^-4, the coding gain of R-S (31, 15, 8) using m = 8 can be up to 2dB. Compared to the R-S (31, 15, 17) code using m = 5 [10], when the E_b/N₀ is fixed at 5dB, the error probability of is 10^-2; and the error probability in this article is 10^-3, indicating that the R-S (31, 15, 8) implemented in this study has better correction capacity.