A hierarchical butterfly-based photonic Network-on-Chip

The demand of high-performance, scalable and energy-efficient on-chip interconnection network are growing in many-core processors. However, the limitations of the metallic interconnect make electronic Network-on-Chip inefficient. Photonic on-chip networks with advanced CMOS-compatible photonic devices, brings a bright future. In this paper, we present a hierarchical butterfly-based photonic Network-on-Chip, with hybrid router, its topology, and the communication protocol. The proposed network leverages the electronic and photonic technology to improve on-chip network performance. HBPNoC uses hierarchical architecture for packet switching in intra-cluster networks and circuit switching in the inter-cluster network. A butterfly-based structure, comprised of 2×2 photonic switching elements, is used for inter-cluster communication. The simulation results show that our proposed network has very good performance with low optical loss.