DocumentCode :
604647
Title :
A high speed binary floating point multiplier using Dadda algorithm
Author :
Jeevan, B. ; Narender, S. ; Reddy, C.V.K. ; Sivani, K.
fYear :
2013
fDate :
22-23 March 2013
Firstpage :
455
Lastpage :
460
Abstract :
This paper presents a high speed binary floating point multiplier based on Dadda Algorithm. To improve speed multiplication of mantissa is done using Dadda multiplier replacing Carry Save Multiplier. The design achieves high speed with maximum frequency of 526 MHz compared to existing floating point multipliers. The floating point multiplier is developed to handle the underflow and overflow cases. To give more precision, rounding is not implemented for mantissa multiplication. The multiplier is implemented using Verilog HDL and it is targeted for Xilinx Virtex-5 FPGA. The multiplier is compared with Xilinx floating point multiplier core.
Keywords :
field programmable gate arrays; floating point arithmetic; hardware description languages; Dadda algorithm; Verilog HDL; Xilinx Virtex-5 FPGA; Xilinx floating point multiplier core; carry save multiplier; frequency 526 MHz; high speed binary floating point multiplier; mantissa speed multiplication; overflow case; underflow case; Adders; Bismuth; Calculators; Field programmable gate arrays; Logic gates; Pipeline processing; Radiation detectors; Dadda Algorithm; FPGA; Floating point; Verilog HDL; multiplication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), 2013 International Multi-Conference on
Conference_Location :
Kottayam
Print_ISBN :
978-1-4673-5089-1
Type :
conf
DOI :
10.1109/iMac4s.2013.6526454
Filename :
6526454
Link To Document :
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