Implementation of binary to floating point converter using HDL

Computation with floating point arithmetic is an indispensable task in many VLSI applications and accounts for almost half of the scientific operation. Also adder is the core element of complex arithmetic circuits, in which inputs should be given in standard IEEE 754 format. The main objective of the work is to design and implement a binary to IEEE 754 floating point converter for representing 32 bit single precision floating point values. The converter at the input side of the existing floating point adder/subtractor module helps to improve the overall design. The modules are written using Very High Speed Integrated Circuit(VHSIC) Hardware Description Language (VHDL), and are then synthesized for Xilinx Virtex E FPGA using Xilinx Integrated Software Environment(ISE) design suite 10.1.