Title :
Thermal design guidelines for a three-dimensional (3D) chip stack, including cooling solutions
Author :
Matsumoto, Kaname ; Ibaraki, S. ; Sueoka, Kazuhisa ; Sakuma, Keita ; Kikuchi, Hiroaki ; Orii, Y. ; Yamada, Fumihiko ; Fujihara, K. ; Takamatsu, Jun ; Kondo, K.
Author_Institution :
ASET (Assoc. of Super-Adv. Electron. Technol.), NANOBIC, Kawasaki, Japan
Abstract :
The thermal resistance of a three-dimensional (3D) chip stack is evaluated, based on the measured thermal resistances of 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. It is discussed how much heat generation of a 3D chip stack is permitted, when a conventional cooling from the top of a 3D chip stack is assumed. Also, as an additional cooling solution for a 3D chip stack, cooling though a laminate (organic substrate) is considered, and the thermal resistance dependence of a laminate on the thermal via density is experimentally clarified. Based on its measured thermal resistance, it is investigated how much additional heat generation is allowed by cooling through a laminate.
Keywords :
cooling; integrated circuit design; laminates; p-n junctions; thermal resistance measurement; three-dimensional integrated circuits; PN junction diodes; cooling solutions; diffused resistors; heating; laminate; temperature sensors; thermal design guidelines; thermal resistance; thermal via density; three-dimensional chip stack; Cooling; Electrical resistance measurement; Laminates; Silicon; Thermal resistance; Three-dimensional displays; Three-dimensional (3D) chip stack; cooling solution; laminate (organic substrate); thermal resistance; thermal via;
Conference_Titel :
Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2013 29th Annual IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-6427-0
Electronic_ISBN :
1065-2221
DOI :
10.1109/SEMI-THERM.2013.6526797
