DocumentCode
605199
Title
FPGA Based Elevator Controller with Improved Reliability
Author
Ekanayake, S. ; Ekanayake, R. ; Sanjayan, S. ; Abeyratne, S.G. ; Dewasurendra, S.D.
Author_Institution
Dept. of Electr. & Electron. Eng., Univ. of Peradeniya, Peradeniya, Sri Lanka
fYear
2013
fDate
10-12 April 2013
Firstpage
260
Lastpage
265
Abstract
This paper introduces a novel method to improve the reliability of a reconfigurable FPGA based elevator controller, which can be used for an elevator with any number of floors, with specified inputs and outputs. It was clear that by simply changing a variable in the HDL code the controller can be generated for an elevator with required number of floors. Thus in this paper the primary implementation and verification procedure is given in detail together with a method to improve the reliability. The flexibility in expansion of designs in an FPGA was considered thoroughly in the proposed reliability improving method. The controller was developed using Verilog HDL throughout the research and a description on the code development is included in the paper. The controller generated was successfully implemented on a Xilinx Spartan 3AN FPGA and tested for a prototype elevator with three floors.
Keywords
field programmable gate arrays; hardware description languages; lifts; reliability; HDL code; Verilog HDL; Xilinx Spartan 3AN FPGA; code development; floor; reconfigurable FPGA based elevator controller; reliability improving method; verification procedure; Elevators; Field programmable gate arrays; Floors; Hardware design languages; Registers; Reliability; Vectors; Elevator; FPGA; Verilog; reconfigurable;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Modelling and Simulation (UKSim), 2013 UKSim 15th International Conference on
Conference_Location
Cambridge
Print_ISBN
978-1-4673-6421-8
Type
conf
DOI
10.1109/UKSim.2013.128
Filename
6527425
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