Enhanced Cycle Simulator for MIPS Architecture -- CSMIPSA

Detailed modeling of processors and cycle accurate simulators are essential for today´s hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we describe the simulator designed by us focused on cycle based approach for instruction execution for the reference MIPS®32 Architecture. This simulator models the extensive user interface based interpretation (three tiered) approach for simulating instruction set for MIPS®32 Architecture in complete Object Oriented Paradigm/Design space. It allows the user to examine the internal state of the target machine, such as the values of processor registers during the execution of each instruction, thereby helping to validate the processor design, the compiler design, as well as evaluate architectural design decisions & provides all the quality metrics of an Instruction Set Architecture(ISA) design explicitly.