New synthesis approach of hierarchical benchmarks for hardware prototyping

Hardware prototyping is becoming increasingly important in the system on chip design cycle. It allows a fast hardware verification within the time to market constraints before reaching the manufacturing phase. However, in the prototyping cycle, designs must be synthesized and mapped into logic gates. The synthesis runtime is very big and does not satisfies the hardware prototyping goals. In this paper we propose a new synthesis methodology which reduces the traditional synthesis runtime. This approach can automatically synthesize large and hierachical designs with a compromise between runtime and optimization. Experimentally, this new approach offers an improvement by an average of 60% compared to the synthesis runtime of an existing commercial tool.