EPC Class 1 GEN 2 UHF RFID tag emulator for robustness evaluation and improvement

Author

Abdelmalek, O. ; Hely, D. ; Beroulle, V.

Author_Institution

Grenoble Inst. of Technol., Valence, France

fYear

2013

fDate

26-28 March 2013

Firstpage

20

Lastpage

24

Abstract

RFID ICs such as EPC Class 1 GEN2 tag are low cost tags which are in some cases used for critical or secure applications. Increasing their robustness is not trivial due to the wide range of error sinks (EM perturbations, attacks...). Moreover increasing the robustness must have a minimum impact on the die area but also must fit with a standardized protocol. In this work we propose a design methodology in order to develop hardened digital tag architecture with a dedicated verification environment taking into account all RFID system parameters

Keywords

integrated circuit design; integrated circuit reliability; integrated circuit testing; radiofrequency identification; radiofrequency integrated circuits; EPC class 1 GEN 2 UHF RFID tag emulator; RFID IC; RFID system parameter; design methodology; hardened digital tag architecture; robustness evaluation; verification environment; Decision support systems; Diffusion tensor imaging; Nanoscale devices; EPC; FPGA prototype; Fault Injection; RFID Security; RFID attacks; Robust IC; Secure IC;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2013 8th International Conference on

Conference_Location

Abu Dhabi

Print_ISBN

978-1-4673-6039-5

Electronic_ISBN

978-1-4673-6038-8

Type

conf

DOI

10.1109/DTIS.2013.6527771

Filename

6527771