Comparator-multiplexer based 6 bit 1.4GSPS low power ADC

Author

Saloni ; Goswami, Mausumi ; Singh, B. Raja

Author_Institution

Dept. of Microelectron., Indian Inst. of Inf. Technol., Allahabad, India

fYear

2013

fDate

26-28 March 2013

Firstpage

134

Lastpage

139

Abstract

This paper presents a comparator-analog multiplexer based 6 bit analog to digital converter (ADC) using repetitive block of 2*1 multiplexer. The multiplexer is designed using transmission gates while subtractor is designed from a 2 stage op-amp. Such an approach results in high speed and less chip area. The comparator in the proposed work is latch based one making the overall design speed faster. The 6-bit ADC is designed and simulated using MOSIS (AMIS) C5X design kit with 2.5 V supply. The proposed design achieves a maximum speed of 1.4 GSPS and dissipates 14.1 mW of power with INL of 0.43 LSB, DNL of 0.38 LSB, SNR of 35.47 dB and SNDR of 34.29 dB respectively.

Keywords

analogue-digital conversion; comparators (circuits); multiplexing equipment; operational amplifiers; GSPS; MOSIS; analog to digital converter; comparator-multiplexer; low power ADC; op-amp; Decision support systems; Diffusion tensor imaging; Information technology; Microelectronics; Nanoscale devices; Analog to digital Converter; DNL; INL; Multiplexer; Subtractor; high speed comparator;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2013 8th International Conference on

Conference_Location

Abu Dhabi

Print_ISBN

978-1-4673-6039-5

Electronic_ISBN

978-1-4673-6038-8

Type

conf

DOI

10.1109/DTIS.2013.6527793

Filename

6527793