Bottom-up design of a high performance ultra-low power DFT utilizing multiple-VDD, multiple-Vth and gate sizing

This paper focuses on the design of an FFT based on butterfly blocks. FFT algorithm is Radix-2 Decimation in Frequency and implementation is done in fixed point using MATLAB software. The low power characteristics of proposed design is achieved using power gating for switching off the non-critical path multipliers in off periods and holding their output nodes in their previous values. This improves the leakage of the circuit effectively while does not affect the performance. Making all path delays equal to the highest path delay improves the energy consumption without any performance penalty. Another mode of operation is high performance mode which employs low-VT transistors especially in critical path and high-VT transistors in other paths. MATLAB Simulations confirms precision of the design. Finally SNR is found for fixed point and floating point versus word width and number of points of FFT.