Die-to-die and within-die variation extraction for circuit simulation with surface-potential compact model

Author

Ohnari, Y. ; Khan, Adnan Ahmed ; Dutta, Arin ; Miura-Mattausch, M. ; Mattausch, Hans Jurgen

Author_Institution

Res. Inst. for Nanodevice & Bio Syst., Hiroshima Univ., Higashi-Hiroshima, Japan

fYear

2013

fDate

25-28 March 2013

Firstpage

146

Lastpage

150

Abstract

A 65nm CMOS TEG for die-to-die and within-die variation analysis is reported. From measured Vth and Ion variation data of transistor pairs, die-to-die and within-die microscopic-parameter variations of a surface-potential model are extracted. Consideration of only five microscopic parameters is found sufficient to capture the channel-length dependence of these variations.

Keywords

CMOS integrated circuits; circuit simulation; integrated circuit modelling; surface potential; CMOS test structure; channel length dependence; circuit simulation; die-to-die variation analysis; size 65 nm; surface potential compact model; within-die variation extraction; Current measurement; MOSFET circuits; Manufacturing; Microscopy; Threshold voltage; Transistors; Voltage measurement; CMOS; Compact Model; Die-To-Die; Macroscopic Parameter; Microscopic Parameter; Surface Potential; Variation; Within-Die;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2013 IEEE International Conference on

Conference_Location

Osaka, Japan

ISSN

1071-9032

Print_ISBN

978-1-4673-4845-4

Electronic_ISBN

1071-9032

Type

conf

DOI

10.1109/ICMTS.2013.6528162

Filename

6528162