DocumentCode :
605539
Title :
BSIM4 parameter extraction for tri-gate Si nanowire transistors
Author :
Tanaka, C. ; Saitoh, Masatoshi ; Ota, Kaoru ; Numata, T.
Author_Institution :
Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan
fYear :
2013
fDate :
25-28 March 2013
Firstpage :
151
Lastpage :
154
Abstract :
We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes using measurement data. Dependence of source/drain parasitic resistances on transistor geometry and fabrication process can be observed on the extracted parameters. Single sets of parameters can reproduce I-V characteristics with Lg down to 35nm.
Keywords :
MOSFET; elemental semiconductors; nanofabrication; nanowires; silicon; BSIM4 parameter extraction procedure; I-V characteristics; Si; measurement data; source-drain parasitic resistances; transistor fabrication processes; transistor geometry; trigate nanowire transistors; Capacitance; Delays; Inverters; Logic gates; MOSFET; Parameter extraction; SPICE; BSIM4; nanowire transistor; parameter extraction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2013 IEEE International Conference on
Conference_Location :
Osaka, Japan
ISSN :
1071-9032
Print_ISBN :
978-1-4673-4845-4
Electronic_ISBN :
1071-9032
Type :
conf
DOI :
10.1109/ICMTS.2013.6528163
Filename :
6528163
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=605539
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