DocumentCode
605547
Title
Tr variance evaluation induced by probing pressure and its stress extraction methodology in 28nm High-K and Metal Gate process
Author
Okagaki, T. ; Hasegawa, T. ; Takashino, H. ; Fujii, Masahiro ; Tsuda, A. ; Shibutani, K. ; Deguchi, Y. ; Yokota, Masao ; Onozawa, K.
Author_Institution
Renesas Electron. Corp., Itami, Japan
fYear
2013
fDate
25-28 March 2013
Firstpage
203
Lastpage
206
Abstract
We discuss characteristics variance in detail, caused by probing stress in 28 nm High-K and Metal Gate process. The Vth variation of nch large size transistor increases by 20% comparing with weak probing pressure (≃ 0). Regarding small size transistors, probing stress impact both on Vth fluctuation and on Tpd fluctuation is small. Moreover, we extracted the space distribution of probing stress quantitatively. It is useful to calibrate a stress simulation methodology and to facilitate evaluation of the mechanical strength of the material.
Keywords
calibration; high-k dielectric thin films; transistors; Tr variance evaluation; calibration; high-k process; metal gate process; probing pressure; probing stress impact; probing stress space distribution; propagation delay characteristic variance; size 28 nm; stress extraction methodology; transistor; Arrays; High K dielectric materials; Logic gates; Metals; Propagation delay; Stress; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures (ICMTS), 2013 IEEE International Conference on
Conference_Location
Osaka, Japan
ISSN
1071-9032
Print_ISBN
978-1-4673-4845-4
Electronic_ISBN
1071-9032
Type
conf
DOI
10.1109/ICMTS.2013.6528172
Filename
6528172
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