Area efficient high speed low power multiplier architecture for multirate filter design

Interpolation and Decimation is very effective and popular in multirate signal processing applications. This paper proposes a high speed, area and power efficient VLSI architecture for polyphase decimation filter with decimation factor of three (D=3) using BFD (Bypass Feed Direct) multiplier. Various key performance metrics such as number of slices, maximum operating frequency, number of LUT´s, input output bonds, power consumption, setup time, hold time, propagation delay between source and destinations are estimated for the filter of length nine (N=9). The power dissipation is reduced in polyphase decimation filter using BFD multiplier which consumes low-power when compared to the conventional multiplier. The speed is improved by using carrylook ahead adder. This architecture also provide significant reduction in area (in terms of number of slices). The proposed scheme has been simulated and the results are reported. It was observed that the proposed scheme provides 57.99% increase in speed, 83.3% reduction in area and slight reduction in power dissipation when compared to conventional multiplier.