A low-power, area efficient design technique for wide fan-in domino logic based comparators

Domino CMOS logic circuits are widely used these days in the design of high-performance modules in modern day integrated chips and microprocessors. The feature of high speed and less area overhead of these logic circuits compared to other logic styles make them a popular choice in the design of high speed circuits. With advancements in high-speed processors, wide fan-in comparators are increasingly being employed in Arithmetic Logic Units (ALUs), Central Processing Units (CPUs). As the process technology and supply voltage are being scaled aggressively, the threshold voltage also has to be scaled down in a similar manner to achieve high performance. With this scaling of threshold voltage, the leakage power increases substantially at ultra deep sub-micron (UDSM) nodes. A circuit level technique has been proposed in this paper for domino logic based wide fan-in 32-bit comparators which incurs minimum area overhead while minimizing leakage & average power consumption with a slight delay penalty. Since, one cannot ignore the growing role of process variations at UDSM nodes, care has been taken to ensure that the overall circuit does not show wide difference in performance under supply voltage, process and temperature fluctuations. The proposed design shows a reduction in active leakage power of nearly 82% when compared to Adaptive Pseudo Dual Keeper (APDK) design and reduction of 66.67% when compared with APDK + leakage tolerant scheme. This design also reduces average power by 84% when compared with the APDK design and by 53.33% when pitted against the APDK + leakage tolerant scheme. Simulations have been carried out using the SILVACO EDA tool at nominal supply voltage of 0.9V, process technology of 32nm and operating frequency of 1.5 GHz.