Implementation of radix-2 and split-radix fast fourier transform algorithm using current mirrors

Implementation of radix-2 and split-radix fast Fourier transform (FFT) algorithm using analog CMOS current mirrors with a reduction in the count of transistors and propagation delay is presented. The proposed method reduces the number of transistors required to implement analog FFTs and the percentage reduction increases considerably for higher point FFTs. It is shown that the number of transistors needed can be reduced further by using the split-radix FFT algorithm for analog implementation. This method decreases the computational delay since transistor count in the critical path gets reduced significantly for higher order FFTs. The work includes simulation and verification of generalized 4-point and 8-point FFT using TANNER EDA tools in 1.25 µm CMOS process. For 256-point FFT, the proposed method has a reduction of 14.76% for radix-2 and 19.03% for split-radix in the transistor count compared to the previous work.