• DocumentCode
    606830
  • Title

    On the crack and delamination risk optimization of a Si-interposer for LED packaging

  • Author

    Auersperg, J. ; Dudek, Rainer ; Jordan, Ramiro ; Bochow-Ness, O. ; Rzepka, S. ; Michel, Bruno

  • Author_Institution
    Micro Mater. Center at Fraunhofer ENAS, Chemnitz, Germany
  • fYear
    2013
  • fDate
    14-17 April 2013
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    3D-integration becomes more and more an important issue for advanced LED packaging solutions as it is a great challenge for the thermo-mechanical reliability to remove heat from LEDs to the environment by heat spreading or specialized cooling technologies. Thermal copper-TSVs provide an elegant solution to effectively transfer heat from LED to the heat spreading structures on the backside of a substrate. But, the use of copper-TSVs generates also novel challenges for reliability as well as also for reliability analysis and prediction, i.e. to manage multiple failure modes acting combined - interface delamination, cracking and fatigue, in particular. In this case, the thermal expansion mismatch between copper and silicon yields to risky stress situations. Therefore, the authors performed extensive simulative work to overcome cracking and delamination risks in the vicinity of thermal copper-TSVs by means of fracture mechanics approaches. Especially, an interaction integral approach is utilized within a simulative DoE and X-FEM is used to help clarifying crack propagation paths in silicon. The DoE-based response surface methodology provided a good insight into the role of model parameters for further optimizations of the intended thermal TSV-approaches in LED packaging applications.
  • Keywords
    cooling; delamination; design of experiments; fatigue cracks; fracture mechanics; integrated circuit packaging; integrated circuit reliability; light emitting diodes; optimisation; response surface methodology; risk analysis; thermal expansion; thermal management (packaging); thermomechanical treatment; three-dimensional integrated circuits; 3D-integration; DoE-based response surface methodology; LED packaging applications; X-FEM; cooling technology; crack propagation paths; crack risk optimization; cracking risk; delamination risk optimization; fatigue; fracture mechanics; heat spreading structures; heat transfer; interaction integral approach; interface delamination; model parameters; multiple failure modes; reliability analysis; reliability prediction; risky stress situations; silicon-interposer; simulative DoE; thermal TSV-approaches; thermal copper-TSV; thermal expansion mismatch; thermo-mechanical reliability; Abstracts; Cooling; Copper; Creep; Germanium; Nickel;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2013 14th International Conference on
  • Conference_Location
    Wroclaw
  • Print_ISBN
    978-1-4673-6138-5
  • Type

    conf

  • DOI
    10.1109/EuroSimE.2013.6529891
  • Filename
    6529891