Title :
Reliability analysis of next generation wafer level chip scale
Author :
Qiuxiao Qian ; Yong Liu
Author_Institution :
Fairchild Semicond., South Portland, ME, USA
Abstract :
In this paper, the reliability performance of next generation WLCSP is studied through modeling. Intensive study is carried out from single bump design to package dimension design and the application design in PCB board. Polyimide, solder joint array layout with different width and length ratio and the PCB board via layout are simulated to improve the reliability performance. The models with different polyimide layouts and different material are studied in both thermal cycling and drop test. Then, the impact of different bump array width and length ratio on the next generation of the WLCSP is studied for the reliability performance. Finally, the impact of different PCB board via design and layout on the reliability performance of next generation WLCSP is analyzed in thermal cycling test. Different through board vias and blind vias array in PCB board are studied.
Keywords :
circuit reliability; polymers; printed circuit design; PCB board; blind vias array; package dimension design; polyimide; reliability analysis; solder joint array layout; thermal cycling test; wafer level chip scale; Abstracts; Arrays; Metals; Polyimides; Semiconductor device reliability; Silicon;
Conference_Titel :
Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2013 14th International Conference on
Conference_Location :
Wroclaw
Print_ISBN :
978-1-4673-6138-5
DOI :
10.1109/EuroSimE.2013.6529987
