FPGA placement by using combined analytical and simulated annealing methods

Nowadays, placement problems become more complex since they need to consider standard cells, mixed size blocks, and area constraints. Analytical placement and simulated annealing placement methods are widely used recently owing to their good performance. But two placement methods have different placement features and characteristics during placement. In this paper, we analyze two different placement algorithms and apply them for FPGA placement capitalizing their advantages. By applying our placement method we could reduce wirelength cost by 9% on the average for a set of benchmark circuits when compared with a well-known commercial placement tool.